The present invention relates to a semiconductor integrated circuit, and more particularly, to a method and apparatus for designing the optimal power supply wiring in a semiconductor integrated circuit and to a recording medium storing a program for performing the method.
The optimization of the widths of power supply lines is important when laying out the power supply lines on an IC chip. Wide power supply lines occupy a large amount of area and thus limit the signal line area and the logic cell area. It is thus preferred that narrow power supply lines be used. However, the amount of current (current capacitance) that flows through a narrow power supply line is small. As a result, a current violation may occur. Current violation refers to a state in which wire breakage or deterioration (electromigration) may occur due to a large amount of current flowing through the line. Further, since the resistance of the line increases as the width of the line is narrowed, a voltage drop that exceeds a certain level (voltage drop violation) occurs. The voltage drop violation may cause the IC to function abnormally. Accordingly, there is a demand for a method that determines the minimum width of the power supply lines without causing a voltage drop violation or a current amount violation.
The optimal power supply line for an IC is one that does not have redundacy and has acceptable current capacitance and voltage drop levels. In a first prior art method for designing the optimal power supply line, the power supply network is analyzed to determine the assumed amount of current that will flow through the line. If the value of the assumed current amount exceeds the current capacitance of the line, the line width is increased from its originally designed width in order to increase the current capacitance. This avoids a current capacitance violation. The power supply network is then analyzed again to check whether the voltage drop is lower than a predetermined limit value. If there is a voltage drop violation, the width of certain lines are increased. Another check for violations is then made. These processes are repeated until the line width is optimized.
However, in the first prior art method, if the width of certain lines are increased to avoid a voltage drop violation when there is no current violation on any of the power supply lines, the increase in the width of the lines is not as effective as it should be for avoiding the voltage drop violation. The rate of current flowing through each power supply line changes by increasing the width of certain lines. As a result, current amount violations may occur at new locations.
In a second prior art method, the widths of all of the lines are increased to avoid voltage drop violations without changing the current rate. However, in this method, the widths of the lines having surplus current capacitance with respect to the actual current amount, or lines having redundant current capacitance are also increased. This increases redundancy and the amount of unnecessarily occupied area.
The second prior art method will now be described with reference to FIGS. 1A and 1B. FIG. 1A shows a power supply wiring having a node N1 connected to a power supply E1 and a node N2 connected to a current supply I1. The nodes N1 and N2 are connected by power supply lines L1, L2, L3. The table of FIG. 1B shows the width and length of each of the lines L1-L3. A current of 2 mA flows through lines L1, L2, and a current of 3 mA flows through line L3. The potential at node N2 is lower than the potential at node N1 by 6 mV. In other words, the voltage drop value of the power supply wiring shown in FIG. 1A is 6 mV.
The voltage drop at node N2 with respect to node N1 may be changed to, for example, 4 mV or lower. Under such condition, if the width of line L2 is doubled, the voltage drop value is 5 mV. If the width of line L1 is doubled, the voltage drop is still no longer 4 mV or lower.
Line Li has a current capacitance of 4 mA. However, since a current of 2 mA flows through line L1, line L1 has extra or redundant capacitance. Thus, an increase in the width of line L1 further increases redundancy. This also increases the amount of current flowing through lines L1, L2 and causes a current amount violation at line L2.
If the width of all of the lines L1, L2, L3 are increased by 1.5 times, the voltage drop value at node N2 is 4 mV. However, this line width increase would further increase the redundancy of lines L1, L3 and the amount of unnecessarily occupied area on the IC chip.
When the width of line L3 is increased by two times, the voltage drop value at node N2 is 3.75 mV, which is an allowable voltage drop level. Thus, in the wiring of FIG. 1A, the most effective way to satisfy the voltage drop reference value is to increase the width of line L3. However, an actual IC is more complicated than the wiring of FIG. 1A. Hence, determining the line which most effectively satisfies the voltage drop standard level when the width is changed is extremely difficult.
In other words, if the width of certain power supply lines are changed, the current amount at other lines changes. This may cause current amount violations at lines whose widths were not changed. Further, the change in voltage drop differs depending on the line whose width is changed. Thus, there may be cases in which power supply drop violations cannot be avoided.
If the width of every line is increased, the current amount rate between each line will not change but the width of lines already having redundancy will be further increased. Accordingly, such wire layout has many redundant portions. If every line width is decreased, the current amount rate between each line will not change, but the lines that do not have redundancy will also be narrowed. Accordingly, current amount violations are apt to occur in such a wire layout.
Additionally, in the prior art, although current amount violation and voltage drop violation were checked, reduction of redundancy in the wiring was difficult.
Accordingly, it is an object of the present invention to provide a method and apparatus for designing the optimal power supply wiring.
To achieve the above object, the present invention provides a design method for optimizing the dimensions of a plurality of power supply lines. The design method includes the steps of analyzing each of the power supply lines, computing a current-capacitance ratio of each of the power supply lines based on the analysis results, and computing a dimension of each of the power supply lines so that the corresponding current-capacitance ratio is within a predetermined range.
Another aspect of the present invention provides a design apparatus for optimizing the dimensions of a plurality of power supply lines. The apparatus includes a processor unit including an analyzing device for analyzing each of the plurality of power supply lines, a first computing device for computing a current-capacitance ratio of each of the power supply lines based on the analysis results, and a second computing device for computing a width of each of the power supply lines so that the corresponding current-capacitance ratio is within a predetermined range.
A further aspect of the present invention provides a computer readable medium for recording a program for optimizing the dimensions of a plurality of power supply lines. The program includes comprising the steps of analyzing each of the plurality of power supply lines, computing a current-capacitance ratio of each of the power supply lines based on the analysis results, and computing a dimension of each of the power supply lines so that the corresponding current-capacitance ratio is included in a predetermined range.
A further aspect of the present invention provides a method for optimally designing a plurality of power supply lines including the steps of checking a current value of each of the plurality of power supply lines, computing a current-capacitance ratio of each of the plurality of power supply lines from an allowable current value of the plurality of power supply lines and the corresponding current value, and computing a dimension of at least one of the plurality of power supply lines so that the corresponding current-capacitance ratio is within a predetermined range.
A further aspect of the present invention provides an apparatus for optimally designing a plurality of power supply lines. The apparatus includes a computation processing unit including a checking device for checking a current value of each of the plurality of power supply lines, a first computing device for computing a current-capacitance ratio of each of the plurality of power supply lines from an allowable current value and the corresponding current value, and a second computing device for computing a dimension of at least one of the plurality of power supply lines so that the corresponding current-capacitance ratio is within a predetermined range.
A further aspect of the present invention provides a computer readable recording medium having recorded thereon program code for optimally designing a plurality of power supply lines. The program code includes means for checking a current value of each of the plurality of power supply lines, means for computing a current-capacitance ratio of each of the power supply lines from an allowable current value and the corresponding current value, and means for computing the dimension of each of the plurality of power supply lines so that the corresponding current-capacitance ratio is within a predetermined range.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.